1. Field of the Invention
The present invention generally relates to semiconductor devices and methods for forming the same, and more particularly relates to a semiconductor device which has a package structure of the BGA (ball grid array) type, and a method for forming the same.
In recent years, there has been an increasing demand for semiconductor devices which can provide an increased packaging density, a higher processing speed, and greater performance. These devices are also required to be implemented in a low cost package structure.
The BGA type package structure has been developed to meet the demands described above, and is used in portable telephones and various other electronic devices.
2. Description of the Related Art
FIG. 1 shows a cross-sectional view of a semiconductor device 1 which has a plastic BGA (hereinafter referred to as PBGA) type package structure of the related art.
In FIG. 1, a printed board 2 has a multilayer structure, and a semiconductor chip 3 is fixed to a mounting surface 2a, which is the upper surface of the printed board 2. An implementing surface 2b opposite the mounting surface 2a of the printed board 2 is provided with a plurality of solder balls 4. The solder balls 4 serve as external-connection nodes.
On both the mounting surface 2a and the implementing surface 2b of the printed board 2 are formed wiring patterns 6a and 6b. The wiring pattern 6a on the mounting surface 2a is connected to the semiconductor chip 3 via wires 5. The wires 5 electrically connect the wiring pattern 6a with the semiconductor chip 3.
The wiring pattern 6a has leads on to the edges of the mounting surface 2a of the printed board 2, and, then, have leads connected to the implementing surface 2b via the side surfaces of the printed board 2. Alternatively, the wiring pattern 6b may have leads connected to the implementing surface 2b via through-holes 6c formed near the perimeter of the printed board 2. Both of these two configurations may coexist, and such a case is shown in FIG. 1. Either via the through-holes 6c or the side surfaces, the wiring pattern 6a is connected to the wiring pattern 6b on the implementing surface 2b, which is in electrical contact with the solder balls 4.
A sealing resin 7 sealing the semiconductor chip 3 is provided over the mounting surface 2a of the printed board 2. The sealing resin 7 is formed in order to protect the semiconductor chip 3, so that the semiconductor chip 3 is buried inside the sealing resin 7.
Forming the semiconductor device 1 in the PBGA structure as described above can provide a reliable implementation even when the number of leads is increased by an increase in the integration density of the semiconductor chip 3. In contrast the QFP (quad flat package) suffers from a degradation of lead strength when there is an increase in the integration density.
In the semiconductor device 1 of the PBGA structure of the related art, the semiconductor chip 3 is mounted on the mounting surface 2a of the printed board 2, and the sealing resin 7 is also mounted over the mounting surface 2a of the printed board 2. That is, the sealing resin 7 is provided only on one side (upper side) of the printed board 2 and the semiconductor chip 3. Unfortunately, this causes a problem when the semiconductor device 1 is subjected to heat in a solder reflow process.
In order to clarify this problem, thermal characteristics of the printed board 2 and the sealing resin 7 will be discussed below.
The printed board 2 is made of glass-epoxy, having a glass transition temperature of 210 (.degree.C.), a thermal-expansion coefficient of 50.times.10.sup.-6 (1/.degree.C.), and a heat conductivity of 5.times.10.sup.-4 (cal/cm.multidot.s.multidot.c). The sealing resin 7 is made of an epoxy-resin, having a glass transition temperature of 150 (.degree.C.), a thermal-expansion coefficient of 15.times.10.sup.-6 (1/.degree.C.), and a heat conductivity of 20.times.10.sup.-4 (cal/cm.multidot.s.multidot.c).
The printed board 2 and the sealing resin 7 differ in their thermal characteristics as described above. Thus, heat applied to the semiconductor device 1 in the solder reflow process at the time of manufacture results in the semiconductor device 1 being bent with edges moving upward as shown by arrows X1 in FIG. 1. This is because the thermal-expansion coefficient of the printed board 2 is larger that of the sealing resin 7. On the other hand, when the semiconductor device 1 is cooled down after the solder reflow process, the semiconductor device 1 is bent with the edges moving downward as shown by arrows X2 in FIG. 1.
In the semiconductor device 1 of the related art, differences in thermal characteristics between the printed board 2 and the sealing resin 7 will cause a bending of the printed board 2 at the time of a temperature increase or a temperature decrease during the solder reflow process. When the edges of the printed board 2 are bent upward (as shown by the arrows X1), the solder balls 4 near the edges of the printed board 2 are expanded in a vertical direction by force generated by the bend. On the other hand, the solder balls 4 around the center of the printed board 2 are contracted from the top by the force generated by the bend. In this manner, the solder balls 4 receive different kinds of force at different locations, so that it becomes difficult to realize reliable solder connections.
Also, a stress is generated by the bend, and is applied to the surface between the printed board 2 and the sealing resin 7. This stress works in such a way as to break the sealing resin 7 off the printed board 2. Thus, cracks may be created on the connecting surface between the printed board 2 and the sealing resin 7, or the sealing resin 7 can be broken off the printed board 2 when the stress is large enough.
In the semiconductor device 1 of the related art, the wiring pattern 6a has leads on to the edges or the proximity of the edges of the mounting surface 2a of the printed board 2, as described above. Then, the wiring pattern 6a is further connected by leads to the implementing surface 2b via the side surfaces of the printed board 2 or the through-holes 6c. In this configuration, the wiring length of the wiring pattern 6a becomes rather long, so that an inductance L of the wiring pattern 6a becomes large. This results in interference between each line segment of the wiring pattern 6a, which decreases performance of the semiconductor device 1. An effect of the interference is particularly strong when the semiconductor chip 3 uses signals having high frequencies for achieving a higher processing speed.
Accordingly, there is a need in the field of semiconductor devices for a semiconductor device in which a stress generated by a difference in thermal-expansion coefficients between the board and the sealing resin is reduced, and for a method for forming the same.
Also, there is a need for a semiconductor device which can improve electrical characteristics of the semiconductor device by shortening a path of a wiring pattern connecting a semiconductor chip and external-connection nodes.